A Standard Cell Based Voter for use in TMR Implementation

For digital circuit/system architectures, the triple modular redundancy (TMR) scheme is widely used to cope with circuit/system faults. The TMR scheme involves duplication of a circuit/system twice and the majority voter, based on Boolean majority logic, ensures that the architecture remains functional even if any copy of circuit/system may become faulty at any time. However, the fundamental assumption remains that the majority voter itself is not faulty. A conventional majority voter has internal nodes/interconnects which if stuck-at some fault might disable the voter or may render the voter partly functional, i.e. correct outputs may be produced only for a subset of inputs. A priority encoding based majority voter was proposed in the literature which supposedly exhibits better fault tolerance than the conventional majority voter. This work shows that not only the conventional majority voter but the priority encoding based majority voter also suffers considerably in the presence of internal stuck-at fault. As a solution, a standard cell based complex gate majority voter is presented in this work which does not feature intermediate output nodes and hence is more robust. All the three majority voters were realized using a cutting-edge 65nm CMOS process technology and the results show that the complex gate majority voter dissipates less power than the conventional and priority encoding based counterparts by 14.2% and 16.3% respectively. Further, the complex gate majority voter encounters reduced delays than the conventional and priority encoding based majority voters by 3.4% and 22.2%, thus featuring optimized power-delay product. Key-Words: Fault tolerance; Triple modular redundancy; Voter; Standard cells; High-speed, Low power.